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LTC2757 1 2757f typical application features applications description 18-bit softspan i out dac with parallel i/o the ltc ? 2757 is an 18-bit multiplying parallel-input, cur- rent-output digital-to-analog converter that provides full 18- bit performanceinl and dnl of 1lsb maximumover temperature without any adjustments. 18-bit monotonicity is guaranteed in all performance grades. this softspan? dac operates from a single 3v to 5v supply and offers six output ranges (up to 10v) that can be programmed through the parallel interface or pin-strapped for operation in a single range. in addition to its precision dc speci? cations, the LTC2757 also offers excellent ac speci? cations, including 2.1s full-scale settling to 1lsb and 1.4nv ? s glitch impulse. the LTC2757 uses a bidirectional input/output parallel interface that allows readback of any on-chip register, including dac output-range settings; and a clr pin and power-on reset circuit that each reset the dac output to 0v regardless of output range. 18-bit voltage output dac with software-selectable ranges n maximum 18-bit inl error: 1 lsb over temperature n program or pin-strap six output ranges: 0v to 5v, 0v to 10v, C2.5v to 7.5v, 2.5v, 5v, 10v n guaranteed monotonic over temperature n low glitch impulse 1.4nv ? s (3v), 3nv ? s (5v) n 18-bit settling time: 2.1s n 2.7v to 5.5v single supply operation n reference current constant for all codes n voltage-controlled offset and gain trims n parallel interface with readback of all registers n clear and power-on-reset to 0v regardless of output range n 48-pin 7mm 7mm lqfp package n instrumentation n medical devices n automatic test equipment n process control and industrial automation LTC2757 integral nonlinearity l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. softspan is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. 150pf + C lt1012 C + lt1468 18-bit dac with span select LTC2757 v osadj r com r in r ofs ref 5v 5v ref r fb i out1 v out i out2 gnd wr upd read d /s clr m-span span i/o s2-s0 gain adjust ge adj 27pf v dd 2757 ta01 wr upd read d /s clr 0.1f data i/o d17-d0 offset adjust code 0 65536 C1.0 inl (lsb) C0.8 C0.6 C0.4 C0.2 0.6 0.4 0.2 0 0.8 1.0 131072 196608 262143 2757 ta01b 10v range 90c 25c C45c
LTC2757 2 2757f absolute maximum ratings i out1 , i out2 , r com to gnd .....................................0.3v r fb , r ofs , r in , ref, v osadj , ge adj to gnd ........... 15v v dd to gnd .................................................. C0.3v to 7v s2, s1, s0, d17-d0 to gnd ............... C0.3v to v dd + 0.3v (7v max) wr , upd, d /s, read, m-span, clr to gnd .................................. C0.3v to 7v operating temperature range LTC2757c .................................................... 0c to 70c LTC2757i..................................................C40c to 85c maximum junction temperature .......................... 150c storage temperature range .................. C65c to 150c lead temperature (soldering, 10 sec)................... 300c order information lead free finish part marking* package description temperature range LTC2757bclx#pbf LTC2757lx 48-lead (7mm 7mm) plastic lqfp 0c to 70c LTC2757bilx#pbf LTC2757lx 48-lead (7mm 7mm) plastic lqfp C40c to 85c LTC2757aclx#pbf LTC2757lx 48-lead (7mm 7mm) plastic lqfp 0c to 70c LTC2757ailx#pbf LTC2757lx 48-lead (7mm 7mm) plastic lqfp C40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ this product is only offered in trays. for more information go to: http://www.linear.com/packaging/ pin configuration (notes 1, 2) 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 r in r in s2 gnd i out2s i out2f gnd d17 d16 d15 d14 d13 13 14 15 16 17 18 19 20 21 22 23 24 d12 d11 d10 d9 v dd gnd gnd clr m-span dnc d8 d7 48 47 46 45 44 43 42 41 40 39 38 37 ge adj r com ref ref r ofs r ofs r fb r fb i out1 v osadj s1 s0 wr upd read d /s dnc d0 d1 d2 d3 d4 d5 d6 top view lx package 48-lead (7mm s 7mm) plastic lqfp t jmax = 150c, ja = 53c/w
LTC2757 3 2757f electrical characteristics v dd = 5v, v(r in ) = 5v unless otherwise speci? ed. the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. symbol param eter conditions LTC2757b LTC2757a units min typ max min typ max static performance resolution l 18 18 bits monotonicity l 18 18 bits dnl differential nonlinearity l 1 0.4 1 lsb inl integral nonlinearity l 2 0.4 1 lsb ge gain error ge adj : 0v, all output ranges l 48 5 32 lsb ge tc gain error temperature coef? cient (note 3) 0.25 0.25 ppm/c bze bipolar zero error all bipolar ranges l 36 3 24 lsb bzs tc bipolar zero temperature coef? cient (note 3) 0.15 0.15 ppm/c psr power supply rejection v dd = 5v, 10% v dd = 3v, 10% l l 1.6 4 0.15 0.4 0.8 2 lsb/v i lkg i out1 leakage current t a = 25c t min to t max l 0.05 2 5 0.05 2 5 na symbol parameter conditions min typ max units analog pins r1, r2 reference inverting resistors (note 4) l 16 20 k r ref dac input resistance (note 5) l 810 k r fb feedback resistor (note 6) l 810 k r ofs bipolar offset resistor (note 6) l 16 20 k r vosadj offset adjust resistor l 1024 1280 k r geadj gain adjust resistor l 2048 2560 k c iout1 output capacitance full-scale zero-scale 90 40 pf pf dynamic performance output settling time span code = 000, 10v step (note 7) to 0.0004% fs 2.1 s glitch impulse v dd = 5v (note 8) v dd = 3v (note 8) 3 1.4 nv? s nv? s digital-to-analog glitch impulse v dd = 5v (note 9) v dd = 3v (note 9) 4 1.8 nv? s nv? s reference multiplying bandwidth 0v to 5v range, code = full-scale, C3db bandwidth 1 mhz multiplying feedthrough error 0v to 5v range, v ref = 10v, 10khz sine wave 0.4 mv thd total harmonic distortion (note 10) multiplying C110 db output noise voltage density (note 11) at i out1 13 nv/ hz v dd = 5v, v(r in ) = 5v unless otherwise speci? ed. the l denotes speci? cations that apply over the full operating temperature range, otherwise speci? cations are at t a = 25c.
LTC2757 4 2757f symbol parameter conditions min typ max units power supply v dd supply voltage l 2.7 5.5 v i dd supply current, v dd digital inputs = 0v or v dd l 0.5 1 a digital inputs v ih digital input high voltage 3.3v v dd 5.5v 2.7v v dd < 3.3v l l 2.4 2 v v v il digital input low voltage 4.5v < v dd 5.5v 2.7v v dd 4.5v l l 0.8 0.6 v v hysteresis voltage 0.1 v i in digital input current v in = gnd to v dd l 1 a c in digital input capacitance v in = 0v (note 12) l 6pf digital outputs v oh i oh = 200a l v dd C 0.4 v v ol i ol = 200a l 0.4 v timing characteristics v dd = 5v, v(r in ) = 5v unless otherwise speci? ed. the l denotes speci? cations that apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. symbol parameter conditions min typ max units v dd = 4.5v to 5.5v write and update timing t 1 i/o valid to wr rising edge set-up l 9ns t 2 i/o valid to wr rising edge hold l 9ns t 3 wr pulse width l 20 ns t 4 upd pulse width l 20 ns t 5 upd falling edge to wr falling edge no data shoot-through l 0ns t 6 wr rising edge to upd rising edge (note 12) l 0ns t 7 d /s valid to wr falling edge set-up time l 9ns t 8 wr rising edge to d /s valid hold time l 9ns readback timing t 13 wr rising edge to read rising edge l 9ns t 14 read falling edge to wr falling edge (note 12) l 20 ns t 15 read rising edge to i/o propagation delay c l = 10pf l 30 ns t 17 upd valid to i/o propagation delay c l = 10pf l 30 ns t 18 d /s valid to read rising edge (note 12) l 9ns t 19 read rising edge to upd rising edge no update l 9ns t 20 upd falling edge to read falling edge no update l 9ns t 22 read falling edge to upd rising edge (note 12) l 9ns t 23 i/o bus hi-z to read rising edge (note 12) l 0ns t 24 read falling edge to i/o bus active (note 12) l 20 ns electrical characteristics v dd = 5v, v(r in ) = 5v unless otherwise speci? ed. the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c.
LTC2757 5 2757f symbol parameter conditions min typ max units clr timing t 25 clr pulse width low l 20 ns v dd = 2.7v to 3.3v write and update timing t 1 i/o valid to wr rising edge set-up l 18 ns t 2 i/o valid to wr rising edge hold l 18 ns t 3 wr pulse width l 30 ns t 4 upd pulse width l 30 ns t 5 upd falling edge to wr falling edge no data shoot-through l 0ns t 6 wr rising edge to upd rising edge (note 12) l 0ns t 7 d /s valid to wr falling edge set-up time l 18 ns t 8 wr rising edge to d /s valid hold time l 18 ns readback timing t 13 wr rising edge to read rising edge l 18 ns t 14 read falling edge to wr falling edge (note 12) l 40 ns t 15 read rising edge to i/o propagation delay c l = 10pf l 48 ns t 17 upd valid to i/o propagation delay c l = 10pf l 48 ns t 18 d /s valid to read rising edge (note 12) l 18 ns t 19 read rising edge to upd rising edge no update l 9ns t 20 upd falling edge to read falling edge no update l 9ns t 22 read falling edge to upd rising edge (note 12) l 18 ns t 23 i/o bus hi-z to read rising edge (note 12) l 0ns t 24 read falling edge to i/o bus active (note 12) l 40 ns clr timing t 25 clr pulse width low l 30 ns note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: continuous operation above the speci? ed maximum operating junction temperature may impair device reliability. note 3: temperature coef? cient is calculated by dividing the maximum change in the parameter by the speci? ed temperature range. note 4: r1 is measured from r in to r com ; r2 is measured from ref to r com . note 5: parallel combination of the resistances from ref to i out1 and from ref to i out2 . dac input resistance is independent of code. note 6 : because of the proprietary softspan switching architecture, the measured resistance looking into each of the speci? ed pins is constant for all output ranges if the i out1 and i out2 pins are held at ground. timing characteristics v dd = 5v, v(r in ) = 5v unless otherwise speci? ed. the l denotes speci? cations that apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. note 7: using lt1468 with c feedback = 27pf. a 0.0004% settling time of 1.8s can be achieved by optimizing the time constant on an individual basis. see application note 120, 1ppm settling time measurement for a monolithic 18-bit dac . note 8: measured at the major carry transition, 0v to 5v range. output ampli? er: lt1468; c fb = 50pf. note 9: zero-code to full-code transition; ref = 0v. falling transition is similar or better. note 10: ref = 6v rms at 1khz. 0v to 5v range. dac code = fs. output ampli? er = lt1468. note 11: calculation from v n = 4ktrb , where k = 1.38e-23 j/k (boltzmann constant), r = resistance ( ), t = temperature (k), and b = bandwidth (hz). note 12: guaranteed by design. not production tested.
LTC2757 6 2757f inl vs temperature dnl vs temperature gain error vs temperature bipolar zero error vs temperature inl vs reference voltage dnl vs reference voltage typical performance characteristics integral nonlinearity (inl) differential nonlinearity (dnl) v dd = 5v, v(r in ) = 5v, t a = 25c, unless otherwise noted. code 0 65536 C1.0 inl (lsb) C0.8 C0.6 C0.4 C0.2 0.6 0.4 0.2 0 0.8 1.0 131072 196608 262143 2757 g01 10v range code 0 65536 C1.0 dnl (lsb) C0.8 C0.6 C0.4 C0.2 0.6 0.4 0.2 0 0.8 1.0 131072 196608 262143 2757 g02 10v range temperature (c) C40 C20 C1.0 inl (lsb) C0.8 C0.6 C0.4 C0.2 0.4 0.2 0 0.6 0.8 1.0 020 +inl Cinl 80 60 40 85 2757 g04 0v to 10v range temperature (c) C40 C20 C1.0 dnl (lsb) C0.8 C0.6 C0.4 C0.2 0.4 0.2 0 0.6 0.8 1.0 020 +dnl Cdnl 80 60 40 85 2757 g05 0v to 10v range temperature (c) C40 C20 C16 ge (lsb) C12 C8 C4 4 0 8 12 16 020 10v 5v 2.5v to 7.5v 2.5v 0v to 5v 0v to 10v 0.25ppm/c typ 80 60 40 85 2757 g06 temperature (c) C40 C20 C16 bze (lsb) C12 C8 C4 4 0 8 12 16 020 10v 5v C2.5v to 7.5v 2.5v 0.15ppm/c typ 80 60 40 85 2757 g07 v(r in ) (v) C10 C2 C6 C4 C1.0 inl (lsb) C0.8 C0.6 C0.2 C0.4 0.4 0.2 0 0.6 0.8 1.0 02 +inl Cinl +inl Cinl 5v range 8 6 410 2757 g08 C8 v(r in ) (v) C10 C2 C6 C4 C1.0 dnl (lsb) C0.8 C0.6 C0.2 C0.4 0.4 0.2 0 0.6 0.8 1.0 02 +dnl Cdnl +dnl Cdnl 5v range 8 6 410 2757 g09 C8 inl vs output range output range C2.5v to 2.5v C2.5v to 7.5v C1.0 inl (lsb) C0.8 C0.6 C0.4 C0.2 0.4 0.2 0 0.6 0.8 1.0 0v to 5v C5v to 5v C10v to 10v 0v to 10v 2757 g03
LTC2757 7 2757f typical performance characteristics settling full-scale step inl vs v dd dnl vs v dd logic threshold vs supply voltage supply current vs logic input voltage supply current vs update frequency mid-scale glitch (v dd = 3v) logic voltage (v) 01 0 i dd (ma) 2 4 6 8 10 12 2345 2757 g16 v dd = 5v v dd = 3v all digital pins tied together (except read tied to gnd) v dd (v) 2.5 0.5 logic threshold (v) 0.75 1 1.25 1.5 2 3 3.5 4 4.5 5 5.5 1.75 2757 g17 rising falling upd frequency (hz) 10 supply current (a) 10 100 100k 1 0.1 100 1k 10k 1m 1000 2757 g18 v dd = 5v v dd = 3v alternating zero-scale/full-scale 500ns/div upd 5v/div gated settling waveform 100v/div (averaged) 2757 g13 lt1468 amp; c feedback = 20pf 0v to 10v step v ref = C10v; span code = 000 t settle = 1.8s to 0.0004% (18 bits) v dd = 5v, v(r in ) = 5v, t a = 25c, unless otherwise noted. v(r in ) (v) 2.5 3.5 4 C1.0 inl (lsb) C0.8 C0.6 C0.2 C0.4 0.4 0.2 0 0.6 0.8 1.0 10v range 5 4.5 5.5 2757 g10 3 +inl Cinl v(r in ) (v) 2.5 3.5 4 C1.0 dnl (lsb) C0.8 C0.6 C0.2 C0.4 0.4 0.2 0 0.6 0.8 1.0 10v range 5 4.5 5.5 2757 g11 3 +dnl Cdnl mid-scale glitch (v dd = 5v) 500ns/div upd 5v/div v out 10mv/div 2757 g14 0v to 5v range lt1468 output amplifier c feedback = 50pf rising major carry transition. falling transition is similar or better. 1.4nv?s typ 500ns/div upd 5v/div v out 10mv/div 2757 g15 0v to 5v range lt1468 output amplifier c feedback = 50pf rising major carry transition. falling transition is similar or better. 3nv?s typ multiplying frequency response vs digital code all bits on all bits off frequency (hz) 100 1k 10k C140 attenuation (db) C100 C120 C60 C80 C40 C20 0 1m 100k 10m 2757 g12 0v to 5v output range lt1468 output amplifier c feedback = 15pf d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
LTC2757 8 2757f pin functions r in (pins 1, 2): input resistor for external reference inverting ampli? er. normally tied to the external reference voltage. typically 5v; accepts up to 15v. these pins are internally shorted together. s2 (pin 3): span i/o bit 2. pins s0, s1 and s2 are used to program and to read back the output range of the dac. see table 2. gnd (pins 4, 7, 18, 19): ground. tie to ground. i out2s , i out2f (pins 5, 6): dac output current comple- ment sense and force pins. tie to ground via a clean, low-impedance path. these pins may also be used with a precision ground buffer amp as a kelvin sensing pair (see the typical applications section). d17-d9 (pins 8-16): dac input/output data bits. these i/o pins set and read back the dac code. d17 (pin 8) is the msb. v dd (pin 17): positive supply input. 2.7v v dd 5.5v. requires a 0.1f bypass capacitor to gnd. clr (pin 20): asynchronous clear input. when clr is asserted low, the dac output resets to v out = 0v. the LTC2757 selects the appropriate reset code according to the active output rangezero-scale for 0v to 5v and 0v to 10v spans, half scale for 2.5v, 5v and 10v spans, or quarter scale for C2.5v to 7.5v span. m-span (pin 21): manual span control input. m-span can be pin-strapped to con? gure the LTC2757 for opera- tion in a single, ? xed output range. to con? gure the part for single-span use, tie m-span directly to v dd . the output range is then set via hardware pin strapping; and the span i/o port ignores write, update and read commands. if m-span is instead connected to ground (softspan con? guration), the output ranges are set and veri? ed by using write, update and read operations. see manual span con? guration in the operation section. m-span must be connected either directly to gnd (for softspan operation) or v dd (for single-span operation). dnc (pins 22, 32): do not connect. d8-d0 (pins 23-31): dac input/output data bits. these i/o pins set and read back the dac code. d0 is the lsb. d /s (pin 33): data/span select input. this pin is used to select activation of the data ( d /s = 0) or span ( d /s = 1) input i/o pins (d0 to d17 or s0 to s2, respectively), along with their respective dedicated registers, for write or read operations. update operations are unaffected by d /s, since all updates affect both data and span registers. for single-span operation, tie d /s to gnd. read (pin 34): read input. when read is asserted high, the data i/o pins (d0-d17) or span i/o pins (s0-s2) out- put the contents of a selected input or dac register (see table 1). data/span ports are selected for readback with the d /s pin; the input/dac registers within those ports are selected for readback with the upd pin. the readback function of the span i/o pins is disabled when m-span is tied to v dd . upd (pin 35): update/register select input. read = low: update function. when upd is asserted high, the contents of the input registers are copied into their respective dac registers. the output of the dac is updated, re? ecting the new dac register values. read = high: register selector function. the update func- tion is disabled and the upd pin functions as a register selector. upd = low selects input registers for readback, high selects dac registers. see readback in the opera- tion section. wr (pin 36): active-low write input. a write operation copies the data present on the data or span i/o pins (d0- d17 or s0-s2, respectively) into the input register. the write function is disabled when read is high. s0 (pin 37): span i/o bit 0. pins s0, s1 and s2 are used to program and to read back the output range of the dac. see table 2. s1 (pin 38): span i/o bit 1. pins s0, s1 and s2 are used to program and to read back the output range of the dac. see table 2.
LTC2757 9 2757f pin functions v osadj (pin 39): dac offset adjust pin. this voltage-control pin can be used to null unipolar offset or bipolar zero error. the offset change expressed in lsb is the same for any output range. see system offset and gain adjustments in the operation section. tie to ground if not used. i out1 (pin 40): dac current output; normally tied to the negative input (summing junction) of the i/v converter ampli? er. r fb (pins 41, 42): dac feedback resistor. normally tied to the output of the i/v converter ampli? er. the dac output current from i out1 ? ows through the feedback resistor to the r fb pins. these pins are internally shorted together. r ofs (pins 43, 44): bipolar offset network. these pins provide the translation of the output voltage range for bipolar spans. accepts up to 15v; normally tied to the positive reference voltage. these pins are internally shorted together. ref (pins 45, 46): feedback resistor for the reference inverting ampli? er, and reference input for the dac. normally tied to the output of the reference inverting ampli? er. typically C5v; accepts up to 15v. these pins are internally shorted together. r com (pin 47): center tap point of r in and ref. normally tied to the negative input of the external reference invert- ing ampli? er. ge adj (pin 48): gain adjust pin. this voltage-control pin can be used to null gain error or to compensate for reference errors. the gain error change expressed in lsb is the same for any output range. see system offset and gain adjustments in the operation section. tie to ground if not used. 36 35 34 33 20 21 18-bit dac with span select dac register input register r com r in 1, 2 r2 20k r1 20k r ofs 43, 44 ref 45, 46 r fb 41, 42 i out1 v osadj 2.56m i out2f i out2s wr upd read d /s clr m-span 2757 bd control logic 3 3 3 i/o port dac register input register 18 18 18 i/o port 40 39 47 ge adj 48 6 5 3, 37, 38 span i/o s2-s0 8-16, 23-31 data i/o d17-d0 block diagram
LTC2757 10 2757f timing diagrams write, update and clear timing readback timing clr wr 2757 td01 t 3 t 6 t 5 t 7 t 8 t 4 t 2 t 1 i/o input upd valid valid d /s t 25 wr 2757 td02 i/o output i/o input read upd d /s t 13 t 23 t 15 t 19 t 17 t 20 t 22 t 18 t 14 t 24 valid valid valid
LTC2757 11 2757f operation to make both registers transparent for ? owthrough mode, tie wr low and upd high. however, this defeats the deglitcher operation and output glitch impulse may increase. the deglitcher is activated on the rising edge of the upd pin. the interface also allows the use of the input and dac registers in a master-slave, or edge-triggered, con? gura- tion. this mode of operation occurs when wr and upd are tied together and driven by a single clock signal. the data bits are loaded into the input register on the falling edge of the clock and then loaded into the dac register on the rising edge. it is possible to control both ports on one 18-bit wide data bus by allowing span pins s2 to s0 to share bus lines with the data lsbs (d2 to d0). no write or read operation acts on both span and data, so there cannot be a signal con? ict. the asynchronous clear pin ( clr ) resets the LTC2757 to 0v (zero-, half- or quarter-scale code) in any output range. clr resets both the input and dac data registers, but leaves the span registers unchanged. the device also has a power-on reset that initializes the dac to v out = 0v in any output range. the dac powers up in the 0v to 5v range at zero-scale if the part is in softspan con? guration. for manual span (m-span tied to v dd ; see manual span con? guration ), the dacs power-up in the manually-chosen range at the appropriate code. manual span con? guration multiple output ranges are not needed in some applica- tions. to con? gure the LTC2757 for single-span opera- tion, tie the m-span pin to v dd and the d /s pin to gnd. the desired output range is programmed by tying s0, s1 and s2 to gnd or v dd (see figure 1 and table 2). in this con? guration, no range-setting software routine is needed; the part will initialize to the chosen output range at power-up, with v out = 0v. when con? gured for manual span operation, span port readback is disabled. output ranges the LTC2757 is a current-output, parallel-input precision multiplying dac offering 1lsb inl and dnl over six software-selectable output ranges. ranges can either be programmed in software for maximum ? exibility or hardwired through pin-strapping. two unipolar ranges are available (0v to 5v and 0v to 10v), and four bipolar ranges (2.5v, 5v, 10v and C2.5v to 7.5v). these ranges are obtained when an external precision 5v reference is used. the output ranges for other reference voltages are easy to calculate by observing that each range is a multiple of the external reference voltage. the ranges can then be expressed: 0 to 1 , 0 to 2 , 0.5 , 1 , 2 , and C0.5 to 1.5 . digital section the LTC2757 has four internal interface registers (see block diagram). two of theseone input and one dac registerare dedicated to the data i/o port, and two to the span i/o port. each port is thus double buffered. double buffering provides the capability to simultaneously update the span and code registers, which allows smooth voltage transitions when changing output ranges. it also permits the simultaneous updating of multiple dacs or other parts on the data bus. write and update operations load the data input register directly from an 18-bit bus by holding the d /s pin low and then pulsing the wr pin low (write operation). load the span input register by holding the d /s pin high and then pulsing the wr pin low (write operation). the span and data register structures are the same except for the number of parallel bitsthe span registers have three bits, while the data registers have 18 bits. the dac registers are loaded by pulsing the upd pin high (update operation), which copies the data held in the input registers of both ports into the dac registers. note that update operations always include both data and span registers; but the dac register values will not change unless the input register values have previously been changed by a write operation.
LTC2757 12 2757f figure 1. con? guring the LTC2757 for single-span operation (10v range) operation the most common readback task is to check the contents of an input register after writing to it, and before updating the new data to the dac register. to do this, hold upd low and assert read high. the contents of the selected ports input register are output to its i/o pins. to read back the contents of a dac register, hold upd low and assert read high, then bring upd high to select the dac register. the contents of the selected dac register are output by the selected ports i/o pins. note: if no update is desired after the readback operation, upd must be returned low before bringing read low, otherwise the upd pin will revert to its primary function and update the dac. table 2. span codes s2 s1 s0 span 0 0 0 unipolar 0v to 5v 0 0 1 unipolar 0v to 10v 0 1 0 bipolar C5v to 5v 0 1 1 bipolar C10v to 10v 1 0 0 bipolar C2.5v to 2.5v 1 0 1 bipolar C2.5v to 7.5v codes not shown are reserved and should not be used. readback the contents of any one of the four interface registers can be read back from the i/o ports by using the read pin in conjunction with the d /s and upd pins. the i/o pins and registers are grouped into two portsdata and span. the data i/o port consists of pins d0-d17, and the span i/o port consists of pins s0, s1 and s2. each i/o port has one dedicated input register and one dedicated dac register. the register structure is shown in the block diagram. a readback operation is initiated by asserting read to logic high after selecting the desired i/o port. select the i/o port (data or span) to be read back with the d /s pin. the selected i/o ports pins become logic outputs during readback, while the unselected i/o ports pins remain high-impedance digital inputs. with the i/o port selected, assert read high and select the desired input or dac register using the upd pin. note that upd is a two function pinthe update function is only available when read is low. if read is high, the update function is disabled and the upd pin instead functions as a register selector, selecting an input or dac register for readback. table 1 shows the readback functions for the LTC2757. table 1. write, update and read functions read d/s wr upd span i/o data i/o 0 0 0 0 - write to input register 0 0 0 1 - write/update (transparent) 0010 - - 0 0 1 1 update dac register update dac register 0 1 0 0 write to input register - 0 1 0 1 write/update (transparent) - 0110 - - 0 1 1 1 update dac register update dac register 1 0 x 0 - read input register 1 0 x 1 - read dac register 1 1 x 0 read input register - 1 1 x 1 read dac register - x = dont care LTC2757 m-span s2 s1 s0 d /s v dd 2757 f01 wr upd read data i/o 18 v dd system offset and gain adjustments many systems require compensation for overall system offset. this may be an order of magnitude or more greater than the offset of the LTC2757, which is so low as to be dominated by external output ampli? er errors even when using the most precise op amps.
LTC2757 13 2757f 1. load 5v range with the output at 0v. note that since span and code are updated together, the output, if started at 0v, will stay there. the 18-bit dac code is shown in hex for compactness. operation wr 2757 td03 span i/o input data i/o input upd d /s 20000 h 010 read = low v out update (5v range, v out = 0v) 0v (00000 h in 0v to 5v range) 0v (20000 h in 5v range) the offset adjust pin v osadj can be used to null unipolar offset or bipolar zero error. the offset change expressed in lsb is the same for any output range: v os lsb [] = ?v(v osadj ) v(r in ) ? 2048 a 5v control voltage applied to v osadj produces v os = C2048 lsb in any output range, assuming a 5v reference voltage at r in . in voltage terms, the offset delta is attenuated by a factor of 32, 64 or 128, depending on the output range. (these functions hold regardless of reference voltage.) v os = C( 1 / 128 )v osadj [0v to 5v, 2.5v spans] v os = C( 1 / 64 )v osadj [0v to 10v, 5v, C2.5v to 7.5v spans] v os = C( 1 / 32 )v osadj [10v span] the gain error adjust pin ge adj can be used to null gain error or to compensate for reference errors. the gain er- ror change expressed in lsb is the same for any output range: ge = v(ge adj ) v(r in ) ? 2048 the gain-error delta is non-inverting for positive reference voltages. note that this pin compensates the gain by altering the inverted reference voltage v(ref). in voltage terms, the v(ref) delta is inverted and attenuated by a factor of 128. v(ref) = C( 1 / 128 )ge adj the nominal input range of these pins is 5v; other volt- ages of up to 15v may be used if needed. however, do not use voltages divided down from power supplies; ref- erence-quality, low-noise inputs are required to maintain the best dac performance. the v osadj pin has an input impedance of 1.28m. this pin should be driven with a thevenin-equivalent impedance of 10k or less to preserve the settling performance of the LTC2757. it should be shorted to gnd if not used. the ge adj pin has an input impedance of 2.56m, and is intended for use with ? xed reference voltages only. it should be shorted to gnd if not used. operationexamples
LTC2757 14 2757f operationexamples 3. write and update mid-scale code in 0v to 5v range (v out = 2.5v) using readback to check the contents of the input and dac registers before updating. wr 2757 td05 data i/o output data i/o input read v out upd d /s 20000 h 20000 h 00000 h hi-z input register dac register hi-z update (2.5v) +2.5v 0v 2. load 10v range with the output at 5v, changing to C5v. wr 2757 td04 span i/o input data i/o input read = low upd d /s 30000 h 10000 h 011 update (5v) update (C5v) +5v C5v v out 0v
LTC2757 15 2757f op amp selection because of the extremely high accuracy of the 18-bit LTC2757, careful thought should be given to op amp selection in order to achieve the exceptional performance of which the part is capable. fortunately, the sensitivity of inl and dnl to op amp offset has been greatly reduced compared to previous generations of multiplying dacs. tables 3 and 4 contain equations for evaluating the ef- fects of op amp parameters on the LTC2757s accuracy. these are the changes the op amp can cause to the inl, dnl, unipolar offset, unipolar gain error, bipolar zero and bipolar gain error. applications information table 3. coef? cients for the equations of table 4 output range a1 a2 a3 a4 a5 5v 1.1 2 1 1 10v 2.2 3 0.5 1.5 5v 2 2 1 1 1.5 10v 4 4 0.83 1 2.5 2.5v 1 1 1.4 1 1 C2.5v to 7.5v 1.9 3 0.7 0.5 1.5 table 4. easy-to-use equations determine op amp effects on dac accuracy in all output ranges (circuit of page 1). subscript 1 refers to output amp, subscript 2 refers to reference inverting amp. op amp inl (lsb) dnl (lsb) unipolar offset (lsb) bipolar zero error (lsb) unipolar gain error (lsb) bipolar gain error (lsb) v os1 (mv) v os1 ?12.1? 5v v ref ? ? ? ? ? ? v os1 ?3.1? 5v v ref ? ? ? ? ? ? a3?v os1 ?52.4? 5v v ref ? ? ? ? ? ? a3?v os1 ?78.6? 5v v ref ? ? ? ? ? ? v os1 ?52.4? 5v v ref ? ? ? ? ? ? v os1 ?52.4? 5v v ref ? ? ? ? ? ? i b1 (na) i b1 ?0.0012? 5v v ref ? ? ? ? ? ? i b1 ?0.00032? 5v v ref ? ? ? ? ? ? i b1 ?0.524? 5v v ref ? ? ? ? ? ? i b1 ?0.524? 5v v ref ? ? ? ? ? ? i b1 ?0.0072? 5v v ref ? ? ? ? ? ? i b1 ?0.0072? 5v v ref ? ? ? ? ? ? a vol1 (v/mv) a1? 66 a vol1 ? ? ? ? ? ? a2? 6 a vol1 ? ? ? ? ? ? 00 a5? 524 a vol1 ? ? ? ? ? ? a5? 524 a vol1 ? ? ? ? ? ? v os2 (mv) 00 0 a4?v os2 ?52.4? 5v v ref ? ? ? ? ? ? v os2 ?104.8? 5v v ref ? ? ? ? ? ? v os2 ?104.8? 5v v ref ? ? ? ? ? ? i b2 (na) 00 0 a4?i b2 ?0.524? 5v v ref ? ? ? ? ? ? i b2 ?1.048? 5v v ref ? ? ? ? ? ? i b2 ?1.048? 5v v ref ? ? ? ? ? ? a vol2 (v/mv) 00 0 a4? 262 a vol2 ? ? ? ? ? ? 524 a vol2 ? ? ? ? ? ? 524 a vol2 ? ? ? ? ? ?
LTC2757 16 2757f applications information table 5 contains a partial list of ltc precision op amps recommended for use with the LTC2757. the easy-to-use design equations simplify the selection of op amps to meet the systems speci? ed error budget. select the ampli? er from table 5 and insert the speci? ed op amp parameters in table 4. add up all the errors for each category to de- termine the effect the op amp has on the accuracy of the part. arithmetic summation gives an (unlikely) worst-case effect. a root-sum-square (rms) summation produces a more realistic estimate. op amp offset contributes mostly to dac output offset and gain error, and has minimal effect on inl and dnl. for example, consider the LTC2757 in unipolar 5v output range. (note that for this example, the lsb size is 19v.) an op amp offset of 35v will cause 1.8lsb of output offset, and 1.8lsb of gain error; but 0.4lsb of inl, and just 0.1lsb of dnl. while not directly addressed by the simple equations in tables 3 and 4, temperature effects can be handled just as easily for unipolar and bipolar applications. first, consult an op amps data sheet to ? nd the worst-case v os and i b over temperature. then, plug these numbers in the v os and i b equations from table 4 and calculate the tempera- ture-induced effects. for applications where fast settling time is important, ap- plication note 120, 1ppm settling time measurement for a monolithic 18-bit dac , offers a thorough discussion of 18-bit dac settling time and op amp selection. recommendations to achieve the full speci? ed static and dynamic performance of the LTC2757, the lt1468 ampli? er is recommended; it offers a unique combination of fast settling and excel- lent dc precision. when using the lt1468 as an output amp, however, the offset voltage (75v max) must be nulled to avoid degrading the linearity of the LTC2757. the lt1468 datasheet shows how to do this with a digital potentiometer. for dc or low-frequency applications, the ltc1150 is the simplest 18-bit accurate output ampli? er. an auto-zero amp, its exceptionally low offset (10v max) and offset drift (0.01v/c) make nulling unnecessary. note: for swings above 8v, use an lt1010 buffer to boost the load current capability of the ltc1150. the settling of auto-zero amps is a special case; see application note 120, 1ppm settling time measurement for a monolithic 18-bit dac , appendix e, for details. the lt1012 and lt1001 are good intermediate output-amp solutions that achieve moderate speed and good accuracy. they are also excellent choices for the reference inverting ampli? er in ? xed-reference applications. figure 3 shows a composite output ampli? er that achieves fast settling (8s) and very low offset (3v max) without offset nulling. this circuit offers high open-loop gain (1000v/mv min), low input bias current (0.15na max), fast slew rate (25v/s min), and a high gain-bandwidth product (30mhz typ). the high speed path consists of an ltc6240, which is an 18mhz ultra-low bias current ampli? er, followed by an lt1360, a 50mhz fast-slewing ampli? er which provides additional gain and the ability to table 5. partial list of ltc precision ampli? ers recommended for use with the LTC2757 with relevant speci? cations amplifier amplifier specifications v os v i b na a vol v/mv voltage noise nv/ hz current noise pa/ hz slew rate v/s gain bandwidth product mhz t settling with LTC2757 s power dissipation mw ltc1150 10 0.05 5600 90 0.0018 3 2.5 10ms 24 lt1001 25 2 800 10 0.12 0.25 0.8 120 46 lt1012 25 0.1 2000 14 0.02 0.2 1 120 11.4 lt1097 50 0.35 2500 14 0.008 0.2 0.7 120 11 lt1468 75 10 5000 5 0.6 22 90 2.1 117
LTC2757 17 2757f applications information swing to 10v at the output. compensation is taken from the output of the ltc6240, allowing the use of a much larger compensation capacitor than if taken after the gain-of-? ve stage. an ltc2054 auto-zero ampli? er senses the voltage at i out1 and drives the non-inverting input of the ltc6240 to eliminate the offset of the high speed path. the 100:1 attenuator and input ? lter reduce the low frequency noise in this stage while maintaining low dc offset. precision voltage reference considerations much in the same way selecting an operational ampli? er for use with the LTC2757 is critical to the performance of the system, selecting a precision voltage reference also requires due diligence. the output voltage of the LTC2757 is directly affected by the voltage reference; thus, any voltage reference error will appear as a dac output volt- age error. there are three primary error sources to consider when selecting a precision voltage reference for 18-bit appli- cations: output voltage initial tolerance, output voltage temperature coef? cient and output voltage noise. initial reference output voltage tolerance, if uncorrected, generates a full-scale error term. choosing a reference with low output voltage initial tolerance, like the lt1236 (0.05%), minimizes the gain error caused by the reference; however, a calibration sequence that corrects for system zero- and full-scale error is always recommended. a references output voltage temperature coef? cient affects not only the full-scale error, but can also affect the circuits inl and dnl performance. if a reference is chosen with a loose output voltage temperature coef? cient, then the dac output voltage along its transfer characteristic will be very dependent on ambient conditions. minimizing the error due to reference temperature coef? cient can be achieved by choosing a precision reference with a low output voltage temperature coef? cient and/or tightly con- trolling the ambient temperature of the circuit to minimize temperature gradients. as precision dac applications move to 18-bit performance, reference output voltage noise may contribute a dominant share of the systems noise ? oor. this in turn can degrade system dynamic range and signal-to-noise ratio. care should be exercised in selecting a voltage reference with as low an output noise voltage as practical for the system resolution desired. precision voltage references like the lt1236 produce low output noise in the 0.1hz to 10hz region, well below the 18-bit lsb level in 5v or 10v full- scale systems. however, as the circuit bandwidths increase, ? ltering the output of the reference may be required to minimize output noise. table 6. partial list of ltc precision references recommended for use with the LTC2757 with relevant speci? cations reference initial tolerance temperature drift 0.1hz to 10hz noise lt1019a-5, lt1019a-10 0.05% max 5ppm/c max 12v p-p lt1236a-5, lt1236a-10 0.05% max 5ppm/c max 3v p-p lt1460a-5, lt1460a-10 0.075% max 10ppm/c max 20v p-p lt1790a-2.5 0.05% max 10ppm/c max 12v p-p ltc6655-2.5 ltc6655-5 0.025% max 2ppm/c max 0.62v p-p grounding as with any high-resolution converter, clean grounding is important. a low-impedance analog ground plane is nec- essary, as are star grounding techniques. keep the board layer used for star ground continuous to minimize ground resistances; that is, use the star-ground concept without using separate star traces. the i out2 pins are of particular concern; inl will be degraded by the code-dependent currents carried by the i out2f and i out2s pins if voltage drops to ground are allowed to develop. the best strategy here is to tie the pins to the star ground plane by multiple vias located directly underneath the part. alternatively, the pins may be routed to the star ground point if necessary; join them together at the part and route a single trace of no more than 30 squares of 1oz copper. in the rare case in which neither of these alternatives is practicable, a force/sense ampli? er should be used as a ground buffer (see the typical applications section). note, however, that the voltage offset of the ground buffer amp directly contributes to the effects on accuracy speci? ed in table 4 under v os1 . the combined effects of the offsets can be calculated by substituting the total offset from i out1 to i out2s for v os1 in the equations.
LTC2757 18 2757f typical applications figure 2. basic connections for softspan v out dac with two optional circuits for driving i out2 from gnd with a force/sense ampli? er + C u2 lt1012 C + u1 lt1468 18-bit dac with span select LTC2757 v osadj v osadj r com 47 48 r in 1, 2 5 7 6 2 8 1 3 4 r2 r1 ge adj 45, 46 r ofs 43, 44 ref 5v 5v 15v ref r fb i out1 v out 41, 42 40 i out2 gnd wr upd read d /s clr m-span 5, 6 4, 7 36 35 34 33 20 21 3, 37, 38 c2 150pf span i/o s2-s0 c1 27pf v dd 17 wr upd read d /s clr c3 0.1f 0.1f 3 8-16, 23-31 39 data i/o d17-d0 16 C + 6 6 5 1 23 i out2f i out2s 2 3 *schottky barrier diode for multiplying applications, u2 = lt1468 and c2 = 15pf zetex* bat54s lt1012 2757 f02 1000pf alternate amplifier for optimum settling time performance 6 6 1 23 5 C + lt1468 3 zetex bat54s 2 200 200 i out2s i out2f C15v 0.1f
LTC2757 19 2757f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description lx package 48-lead plastic lqfp (7mm 7mm) (reference ltc dwg # 05-08-1760 rev ?) lx48 lqfp 0907 rev? 0 ? 7 11 ? 13 0.45 ? 0.75 1.00 ref 11 ? 13 9.00 b s c aa 7.00 b s c 1 2 7.00 b s c 9.00 b s c 48 1.60 max 1.35 ? 1.45 0.05 ? 0.15 0.09 ? 0.20 0.50 b s c 0.17 ? 0.27 gauge plane 0.25 note: 1. package dimen s ion s conform to jedec #m s -026 package outline 2. dimen s ion s are in millimeter s 3. dimen s ion s of package do not include mold fla s h. mold fla s h s hall not exceed 0.25mm on any s ide, if pre s ent 4. pin-1 indentifier i s a molded indentation, 0.50mm diameter 5. drawing i s not to s cale s ee note: 4 c0.30 ? 0.50 r0.08 ? 0.20 7.15 ? 7.25 5.50 ref 1 2 5.50 ref 7.15 ? 7.25 48 package outline recommended s older pad layout apply s older ma s k to area s that are not s oldered s ection a ? a 0.50 b s c 0.20 ? 0.30 1.30 min
LTC2757 20 2757f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2010 lt 0410 ? printed in usa related parts typical application part number description comments ltc1591/ ltc1597 parallel 14-/16-bit i out single dac integrated 4-quadrant resistors ltc1592 serial 16-bit i out single dac software-selectable (softspan) ranges, 1lsb inl, dnl, 16-lead ssop package ltc1821 parallel 16-bit v out single dac 1lsb inl, dnl, 0v to 10v, 0v to C10v, 10v output ranges ltc2641/ ltc2642 serial 12-/14-/16-bit unbuffered v out single dacs 1lsb inl, 1lsb dnl, 1s settling, tiny msop-10, 3mm 3mm dfn-10 packages ltc2704 serial 12-/14-/16-bit v out softspan quad dacs software-selectable ranges, integrated ampli? ers ltc2751 parallel 12-/14-/16-bit i out softspan single dac 1lsb inl, dnl, software-selectable ranges, 5mm 7mm qfn-38 package ltc2753 parallel 12-/14-/16-bit i out softspan dual dacs 1lsb inl, dnl, software-selectable ranges, 7mm 7mm qfn-48 package ltc2754 serial 12-/16-bit i out softspan quad dacs 1lsb inl, dnl, software-selectable ranges, 7mm 8mm qfn-52 package ltc2755 parallel 12-/14-/16-bit i out softspan quad dacs 1lsb inl, dnl, software-selectable ranges, 9mm 9mm qfn-64 package lt1027 precision reference 1ppm/c maximum drift lt1236a-5 precision reference 0.05% maximum tolerance, 1ppm 0.1hz to 10hz noise ltc1150 15v zero-drift op amp 10v maximum offset voltage, 1.8v p-p (0.1hz to 10hz) noise, 0.8ma supply current lt1468 16-bit accurate op amp 90mhz gbw, 22v/s slew rate 100pf 10k 15v 12v C15v + C lt1012 LTC2757 to microcontroller ge adj ref ref r fb r fb r ofs r ofs v dd r in r in r com read m-span gnd gnd gnd d /s upd wr clr i out1 i out2f i out2s gnd v osadj 2757 f03 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 s2 s1 s0 5v C5v C + ltc2054 + C ltc1360 15v C15v 5v C5v C + ltc6240 1k 10k 1f 1k 10 1f 5pf 4.02k 1k 100pf ltc6655-5 in out 10f v out 0.1f figure 3. composite ampli? er provides 18-bit precision and fast settling

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